[PATCH] D94144: [RISCV] Support vscale intrinsic and ISDNode.

[Hsiangkai Wang via Phabricator via llvm-commits]

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In RISC-V, we have VLENB register to know the real vector size at run time. `vscale` is the run time constant in LLVM to know the factor in the scalable vector types. We could use VLENB to get `vscale` value in LLVM.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94144

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll

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