[PATCH] D93791: [AArch64] Add Fujitsu A64FX scheduling model

[KAWASHIMA Takahiro via Phabricator via llvm-commits]

kawashima-fj marked an inline comment as done.
kawashima-fj added a comment.

In D93791#2471417 <https://reviews.llvm.org/D93791#2471417>, @tschuett wrote:

> Is there a way to specify the maximum or even the set of supported SIMD-widths for SVE cores?

@tschuett 
I think there is no field to specify the maximum SIMD-width in the machine model.

`llvm/lib/Target/AArch64/AArch64Subtarget.cpp` has `cl::opt<unsigned> SVEVectorBitsMax` variable. Specifying `-aarch64-sve-vector-bits-max=...` option can set the value at the application compile time. However, the `SVEVectorBitsMax` is not used anywhere in the LLVM code currently.

What is the intent of the question? Suggestion to specify it in the machine model? If so, we can add the field when a usage comes up.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93791/new/

https://reviews.llvm.org/D93791