[PATCH] D93791: [AArch64] Add Fujitsu A64FX scheduling model

[KAWASHIMA Takahiro via Phabricator via llvm-commits]

kawashima-fj marked an inline comment as done.
kawashima-fj added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA64FX.td:102
+
+def A64FXAny : ProcResGroup<[A64FXIPFLA, A64FXIPPR, A64FXIPEXA, A64FXIPFLB,
+                             A64FXIPEXB, A64FXIPEAGA, A64FXIPEAGB, A64FXIPBR]> {
----------------
dmgreen wrote:
> Is this used anywhere? If so, for what?
`A64FXAny` is not used elsewhere explicitly but removing it causes the following TableGen error. `CodeGenSchedModels::verifyProcResourceGroups` function in `llvm/utils/TableGen/CodeGenSchedule.cpp` emits this error.

```
$ $build/NATIVE/bin/llvm-tblgen -gen-subtarget
    -I $src/llvm/lib/Target/AArch64 -I$build/include -I$src/llvm/include
    -I $src/llvm/lib/Target $src/llvm/lib/Target/AArch64/AArch64.td
    --write-if-changed -o lib/Target/AArch64/AArch64GenSubtargetInfo.inc
    -d lib/Target/AArch64/AArch64GenSubtargetInfo.inc.d
Included from $src/llvm/lib/Target/AArch64/AArch64.td:556:
$src/llvm/lib/Target/AArch64/AArch64SchedA64FX.td:80:1:
  error: proc resource group overlaps with A64FXGI02 but no supergroup contains both.
def A64FXGI01 : ProcResGroup<[A64FXIPFLA, A64FXIPPR]>;
^
```

Does anyone know why this overlaping check exists?

`llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td` also has `THX2T99Any` and `llvm/lib/Target/X86/X86Sched*.td` also have `*PortAny`. I copied it.



================
Comment at: llvm/lib/Target/AArch64/AArch64Schedule.td:35
 def WriteID64      : SchedWrite; // 64-bit Divide
+def WriteID512     : SchedWrite; // 512-bit Divide
 def ReadID         : SchedRead;  // 32/64-bit Divide
----------------
dmgreen wrote:
> What is this for? It doesn't appear to be used in any instructions.
It was my mistake. `WriteID512` was not needed. I removed it in the latest patch. Thanks.


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https://reviews.llvm.org/D93791