[PATCH] D93804: [RISCV] Spilling for RISC-V V extension.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:97
+  // enabled. See llvm/test/CodeGen/RISCV/rvv/spill-vector-csr.ll.
+  if (TFI->hasFP(MF) || Subtarget.hasStdExtV())
     markSuperRegs(Reserved, RISCV::X8); // fp
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Should `hasFP` not pessimistically return true if V is enabled?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93804/new/

https://reviews.llvm.org/D93804