[PATCH] D93867: [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: khchen, HsiangKai.
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The spec for these instructions include this note. "The destination register
cannot overlap either the source register or the mask register ('v0') if the
instruction is masked." So we need earlyclobber to enforce this constraint.

I've regenerated the tests with update_llc_test_checks.py to show the
effects of the earlyclobber.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93867

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll

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