[PATCH] D93859: [GlobalISel][TableGen] Add BitsPerByte value

[Gabriel Hjort Åkerlund via Phabricator via llvm-commits]

ehjogab created this revision.
ehjogab added reviewers: dsanders, arsenm, ab, qcolombet, bjope, Paul-C-Anagnostopoulos.
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In some targets, the smallest addressable unit does not consist of 8
bits. For such targets, the matcher code for G_SEXTLOAD and G_ZEXTLOAD
is incorrect and never yield a match. This patch addresses this problem
by introducing a new value BitsPerByte, thereby allowing the 8-bit
assumption to be removed from TableGen.

Change-Id: Ic6a3e6976a960c8ef65b4a7dbb065b2529d07dd9


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93859

Files:
  llvm/include/llvm/Target/Target.td
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/CodeGenTarget.h
  llvm/utils/TableGen/GlobalISelEmitter.cpp


Index: llvm/utils/TableGen/GlobalISelEmitter.cpp
===================================================================
--- llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -3813,10 +3813,13 @@
       // MMO's work in bytes so we must take care of unusual types like i1
       // don't round down.
       unsigned MemSizeInBits =
-          llvm::alignTo(MemTyOrNone->get().getSizeInBits(), 8);
+          llvm::alignTo(MemTyOrNone->get().getSizeInBits(),
+                        Target.getBitsPerByte());
 
-      InsnMatcher.addPredicate<MemorySizePredicateMatcher>(0,
-                                                           MemSizeInBits / 8);
+      InsnMatcher
+          .addPredicate<MemorySizePredicateMatcher>(0,
+                                                    MemSizeInBits /
+                                                    Target.getBitsPerByte());
       return InsnMatcher;
     }
   }
@@ -6168,3 +6171,4 @@
   GlobalISelEmitter(RK).run(OS);
 }
 } // End llvm namespace
+
Index: llvm/utils/TableGen/CodeGenTarget.h
===================================================================
--- llvm/utils/TableGen/CodeGenTarget.h
+++ llvm/utils/TableGen/CodeGenTarget.h
@@ -86,6 +86,10 @@
   ///
   bool getAllowRegisterRenaming() const;
 
+  /// getBitsPerByte - Return the BitsPerByte int value for this target.
+  ///
+  int getBitsPerByte() const;
+
   /// getAsmParser - Return the AssemblyParser definition for this target.
   ///
   Record *getAsmParser() const;
Index: llvm/utils/TableGen/CodeGenTarget.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenTarget.cpp
+++ llvm/utils/TableGen/CodeGenTarget.cpp
@@ -293,6 +293,10 @@
   return TargetRec->getValueAsInt("AllowRegisterRenaming");
 }
 
+int CodeGenTarget::getBitsPerByte() const {
+  return TargetRec->getValueAsInt("BitsPerByte");
+}
+
 /// getAsmParser - Return the AssemblyParser definition for this target.
 ///
 Record *CodeGenTarget::getAsmParser() const {
Index: llvm/include/llvm/Target/Target.td
===================================================================
--- llvm/include/llvm/Target/Target.td
+++ llvm/include/llvm/Target/Target.td
@@ -1525,6 +1525,10 @@
   // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
   // for all opcodes if this flag is set to 0.
   int AllowRegisterRenaming = 0;
+
+  // BitsPerByte - Specifies the size (in bits) of the smallest addressable
+  // unit in the target. Typically this is 8 bits, which is the default value.
+  int BitsPerByte = 8;
 }
 
 //===----------------------------------------------------------------------===//


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