[PATCH] D93843: [RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) isel patterns.

[Craig Topper via Phabricator via llvm-commits]

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With the i32 these patterns will only fire on RV32, but they
don't look RV32 specific.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93843

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/vararg.ll

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