[PATCH] D93750: [RISCV] Frame handling for RISC-V V extension.

[luxufan via Phabricator via llvm-commits]

StephenFan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:547
     const RISCVRegisterInfo *RI = STI.getRegisterInfo();
-    if (RI->needsStackRealignment(MF)) {
+    if (RI->needsStackRealignment(MF) && !MFI.hasScalableVectorObjects()) {
       Align MaxAlignment = MFI.getMaxAlign();
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HsiangKai wrote:
> StephenFan wrote:
> > why if the machine function has the scalable vector objects, then the prolog doesn't need to realign the stack address ?
> I need to think about how to deal with it when there are objects needed realignment and RVV objects on the stack at the same time.
we have an internal implementation that if needs realignment and RVV objects on the stack at the same time. The BP register needs to be used as base address of stack object. So modify the hasBP function in RISCVFrameLowering.cpp may be a good choice. However, maybe there is a better solution.


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https://reviews.llvm.org/D93750