[PATCH] D93746: [RISCV] Define vector single-width reduction intrinsic.

[Monk Chiang via Phabricator via llvm-commits]

monkchiang updated this revision to Diff 313641.
monkchiang added a comment.

Remove redundant constraint in VPseudoReductionV_VS class


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93746/new/

https://reviews.llvm.org/D93746

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll