[PATCH] D93746: [RISCV] Define vector single-width reduction intrinsic.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:932
+    defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass,
+                              m, "@earlyclobber $rd">;
+}
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Is earlyclobber needed for these instructions?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93746/new/

https://reviews.llvm.org/D93746