[PATCH] D93612: [RISCV] Update V instructions constraints to conform to v1.0

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h:93
   // source vector register group or the source mask register
   WidenV = VS2Constraint | VS1Constraint | VMConstraint,
   WidenW = VS1Constraint | VMConstraint,
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These enum values aren't used. Just the ones in X86InstrFormats.td are used and now they aren't in sync.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93612/new/

https://reviews.llvm.org/D93612