[PATCH] D93746: [RISCV] Define vector single-width reduction intrinsic.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll:5
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
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The description in IntrinsicsRISCV.td says "The LMUL of second source vector must be 1."  But this intrinsic has the destination, first, and third sources as LMUL=1 and the second source as LMUL=1/4.

It looks like every test in this file has LMUL=1 destination and the second source vector is the type that varies. So is the comment in IntrinsicsRISCV.td wrong?


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  https://reviews.llvm.org/D93746/new/

https://reviews.llvm.org/D93746