[PATCH] D93746: [RISCV] Define vector single-width reduction intrinsic.

[Monk Chiang via Phabricator via llvm-commits]

monkchiang created this revision.
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Define integer reduction:
vredsum/vredmaxu/vredmax/vredminu/vredmin/vredand/vredor/vredxor
Define float reduction:
vfredosum/vfredsum/vfredmax/vfredmin

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen at sifive.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93746

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll