[PATCH] D93707: [FPEnv] Allow fneg + strict_fsub -> strict_fadd in DAGCombiner

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13416
+    return DAG.getNode(ISD::STRICT_FADD, DL, DAG.getVTList(VT, ChainVT),
+                       {Chain, N0, NegN1}, Flags);
+
----------------
Can we use SelectionDAG::FlagInserter like visitFSUB instead of passing Flags?


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Comment at: llvm/test/CodeGen/X86/fp-intrinsics.ll:70
 ; X87-NEXT:    fldz
-; X87-NEXT:    fsubrl {{[0-9]+}}(%esp)
+; X87-NEXT:    fchs
+; X87-NEXT:    faddl	4(%esp)
----------------
Why did this get worse?


================
Comment at: llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll:680
 define <1 x float> @constrained_vector_fsub_v1f32() #0 {
+; CHECK:       # float -1
 ; CHECK-LABEL: constrained_vector_fsub_v1f32:
----------------
The checks line are normally generated by a script update_llc_test_checks.py. The next time someone reruns that script on this file, theses lines will disappear.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93707/new/

https://reviews.llvm.org/D93707