[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

Mon Dec 21 12:59:15 PST 2020

craig.topper added a comment.

Would it make sense to move the SDNode patterns and their helpers to a different file. They use the pseudos but are otherwise independent. I worry that RISCVInstrInfoVPseudos.td is going to become very large and this might be a logical piece to split out.

================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2186
+foreach vti = AllIntegerVectors in {
+  def : Pat<(vti.Vector (splat_vector GPR:$rs1)),
+            (!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
----------------
frasercrmck wrote:
> One thing I'm not sure about is whether or not to keep `splat_vector` and `rv32_splat_i64` patterns separate as I've done here or whether to use the `ComplexPattern`s as root nodes to combine the two. Assuming `rv32_splat_i64` is only generated for RV32/i64 and `splat_vector` isn't created for that case, the result should be the same if a little less clear.
I think it's fine to keep them separate. It definitely won't save anything in the isel table. Tablegen needs to create a different pattern for each root opcode possibility.

Repository:
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  https://reviews.llvm.org/D93312/new/

https://reviews.llvm.org/D93312