[PATCH] D93624: [RISCV] Fix rounding mode in lowering of float operations

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Doesn't this render `fesetround` useless?



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Comment at: llvm/test/CodeGen/RISCV/double-arith.ll:40
+; RV32IFDIS-LABEL: <fadd_d>:
+; RV32IFDIS:      fadd.d ft0, ft1, ft0, rne
   %1 = fadd double %a, %b
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I don't understand this. Either you're changing CodeGen which should mean the assembly changes or you're changing the assembler which should instead be tested in the MC tests. You should almost never need to disassemble during a CodeGen test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93624/new/

https://reviews.llvm.org/D93624