[PATCH] D93611: [RISCV] Make LMUL field in VTYPE continuous.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h:379
   unsigned VSEWBits = static_cast<unsigned>(VSEW);
-  unsigned VTypeI =
-      ((VLMULBits & 0x4) << 3) | (VSEWBits << 2) | (VLMULBits & 0x3);
+  unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
   if (TailAgnostic)
----------------
I don't think the 0x7 on VLMULBits is necessary. We don't mask VSEWBits here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93611/new/

https://reviews.llvm.org/D93611