[PATCH] D93368: [RISCV] Define vector compare intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:559
+// When the destination EEW is different from source EEW, we need to use
+// @earlyclobber to avoid the overlap between destination and source registers.
+multiclass VPseudoBinaryM_VV {
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craig.topper wrote:
> Is it safe for LMUL=1, 1/2, 1/4, 1/8? Does this criteria from the 1.0 spec only when overlap is ok apply 
> 
> "The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not)."
> 
> For LMUL the source register group is always a single register. So does that mean any overlap would always be in the lowest numbered part?
>From another statement in the same section.

"The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not)."

It is said the source EMUL is at least 1. There is no such constraint when the destination EEW is smaller than the source EEW. I think it is safe for LMUL = 1, 1/2, 1/4, 1/8.

The earlyclobber constraint is too strong for the overlap rules. Regardless fractional LMUL or not, it is not permitted to overlap the lowest numbered part in the implementation.


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