[PATCH] D93368: [RISCV] Define vector compare intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:559
+// When the destination EEW is different from source EEW, we need to use
+// @earlyclobber to avoid the overlap between destination and source registers.
+multiclass VPseudoBinaryM_VV {
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Is it safe for LMUL=1, 1/2, 1/4, 1/8? Does this criteria from the 1.0 spec only when overlap is ok apply 

"The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not)."

For LMUL the source register group is always a single register. So does that mean any overlap would always be in the lowest numbered part?


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https://reviews.llvm.org/D93368