[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1399
+    // accidentally sign-extend the 32-bit halves to the e64 SEW:
+    //   vmv.v.x vX, hi
+    //   vsll.vx vX, vX, /*32*/
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Is it possible to build this sequence from LowerSPLAT_VECTOR using ISD::SHL, ISD::SRL, ISD::OR, RISCVISD::SPLAT_VECTOR_I64, etc? That's probably better than emitting a large sequence in the isel table.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93312/new/

https://reviews.llvm.org/D93312