[PATCH] D92104: [RegisterScavenging] Fix assert in scavengeRegisterBackwards

[Simon Cook via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG698ae90f3062: [RegisterScavenging] Fix assert in scavengeRegisterBackwards (authored by craigblackmore, committed by simoncook).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92104/new/

https://reviews.llvm.org/D92104

Files:
  llvm/lib/CodeGen/RegisterScavenging.cpp


Index: llvm/lib/CodeGen/RegisterScavenging.cpp
===================================================================
--- llvm/lib/CodeGen/RegisterScavenging.cpp
+++ llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -573,9 +573,8 @@
                             RestoreAfter);
   MCPhysReg Reg = P.first;
   MachineBasicBlock::iterator SpillBefore = P.second;
-  assert(Reg != 0 && "No register left to scavenge!");
   // Found an available register?
-  if (SpillBefore == MBB.end()) {
+  if (Reg != 0 && SpillBefore == MBB.end()) {
     LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
                << '\n');
     return Reg;
@@ -584,6 +583,8 @@
   if (!AllowSpill)
     return 0;
 
+  assert(Reg != 0 && "No register left to scavenge!");
+
   MachineBasicBlock::iterator ReloadAfter =
     RestoreAfter ? std::next(MBBI) : MBBI;
   MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);


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