[llvm] 698ae90 - [RegisterScavenging] Fix assert in scavengeRegisterBackwards

[Simon Cook via llvm-commits]

Author: Craig Blackmore
Date: 2020-12-18T16:57:05Z
New Revision: 698ae90f306248aafbfb5c85cdd9bb81c387bb59

URL: https://github.com/llvm/llvm-project/commit/698ae90f306248aafbfb5c85cdd9bb81c387bb59
DIFF: https://github.com/llvm/llvm-project/commit/698ae90f306248aafbfb5c85cdd9bb81c387bb59.diff

LOG: [RegisterScavenging] Fix assert in scavengeRegisterBackwards

According to the documentation, if a spill is required to make a
register available and AllowSpill is false, then NoRegister should be
returned, however, this scenario was actually triggering an assertion
failure.

This patch moves the assertion after the handling of AllowSpill.

Authored by: Lewis Revill

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D92104

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegisterScavenging.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index ab9a1d66b835..ab8f4fd9778b 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -573,9 +573,8 @@ Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
                             RestoreAfter);
   MCPhysReg Reg = P.first;
   MachineBasicBlock::iterator SpillBefore = P.second;
-  assert(Reg != 0 && "No register left to scavenge!");
   // Found an available register?
-  if (SpillBefore == MBB.end()) {
+  if (Reg != 0 && SpillBefore == MBB.end()) {
     LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
                << '\n');
     return Reg;
@@ -584,6 +583,8 @@ Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
   if (!AllowSpill)
     return 0;
 
+  assert(Reg != 0 && "No register left to scavenge!");
+
   MachineBasicBlock::iterator ReloadAfter =
     RestoreAfter ? std::next(MBBI) : MBBI;
   MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);