[PATCH] D93487: [RISCV] Sign extend constant arguments to V intrinsics when promoting to XLen.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D93487#2461366 <https://reviews.llvm.org/D93487#2461366>, @rogfer01 wrote:

>> For instructions that use a uimm5 immediate, this change only affects
>> constants >= 128 for i8 or >= 32768 for i16. Constants that large
>> already wouldn't have been eligible for uimm5 and would need to use a
>> scalar register.
>
> Just to make sure I understand this case, this is relevant for negative numbers which at this point of the backend just look like like very large constants (up to XLenVT).
>
> Other than that, LGTM. Thanks @craig.topper

That was me thinking through making sure this wouldn't break shifts and other instructions that use uimm5. If for some reason an SEW=8 shift had 128 as a constant, previously it would have stayed 128 when we extended it to xlenvt. Now it becomes 0xffffffffffffff80. But neither 128 or 0xffffffffffffff80 would be matched by uimm5 so this shouldn't break those instructions.


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