[PATCH] D93487: [RISCV] Sign extend constant arguments to V intrinsics when promoting to XLen.

[Craig Topper via Phabricator via llvm-commits]

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The default behavior for any_extend of a constant is to zero extend.
This occurs inside of getNode rather than allowing type legalization
to promote the constant which would sign extend. By using sign extend
with getNode the constant will be sign extended. This gives a better
chance for isel to find a simm5 immediate since all xlen bits are
examined there.

For instructions that use a uimm5 immediate, this change only affects
constants >= 128 for i8 or >= 32768 for i16. Constants that large
already wouldn't have been eligible for uimm5 and would need to use a
scalar register.

If the instruction isn't able to use simm5 or the immediate is
too large, we'll need to materialize the immediate in a register.
As far as I know constants with all 1s in the upper bits should
materialize as well or better than all 0s.

Longer term we should probably have a SEW aware PatFrag to ignore
the bits above SEW before checking simm5.

I updated about half the test cases in some tests to use a negative
constant to get coverage for this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93487

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll

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