[PATCH] D93471: [RISCV] Define vlxe/vsxe/vsuxe intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1523
+  // calculate octuple elmul which is (eew * octuple_lmul) >> log_sew
+  defvar octuple_elmul = !sra(!mul(eew, octuple_lmul), log_sew);
+  // legal octuple elmul should be more than 0 and less than eqaul 64
----------------
Why is this !sra not !srl?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1524
+  defvar octuple_elmul = !sra(!mul(eew, octuple_lmul), log_sew);
+  // legal octuple elmul should be more than 0 and less than eqaul 64
+  if !gt(octuple_elmul, 0) then {
----------------
eqaul->equal


Repository:
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  https://reviews.llvm.org/D93471/new/

https://reviews.llvm.org/D93471