[PATCH] D93471: [RISCV] Define vlxe/vsxe/vsuxe intrinsics.

[Zakk Chen via Phabricator via llvm-commits]

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Define vlxe/vsxe intrinsics and lower to vlxei<EEW>/vsxei<EEW> instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93471

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll