[PATCH] D93445: [RISCV] Define vlse/vsse intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:103
+                    [LLVMPointerType<LLVMMatchType<0>>,
+                     llvm_anyint_ty, llvm_anyint_ty],
+                    [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic;
----------------
Is stride and vl both XLenVT? Can we use LLVMMatchType<1> for VL?


================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:111
+                     LLVMPointerType<LLVMMatchType<0>>, llvm_anyint_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic;
----------------
Same here


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll:9
+
+define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i32 %2, i32%3) nounwind {
+entry:
----------------
Missing space between i32 and %3


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93445/new/

https://reviews.llvm.org/D93445