[PATCH] D93132: [SVE][CodeGen] Vector + immediate addressing mode for masked gather/scatter

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin updated this revision to Diff 312226.
kmclaughlin marked 2 inline comments as done.
kmclaughlin added a comment.

- Improve codegen where the splat value is a constant, but out of range for the immediate addressing mode, e.g.

  mov x8, xzr
  add z1.d, z1.d, #32 // =0x20
  st1b { z0.d }, p0, [x8, z1.d]
  ret

->

  mov w8, #32
  st1b { z0.d }, p0, [x8, z1.d]
  ret


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93132/new/

https://reviews.llvm.org/D93132

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
  llvm/test/CodeGen/AArch64/sve-masked-gather-vec-plus-imm.ll
  llvm/test/CodeGen/AArch64/sve-masked-gather-vec-plus-reg.ll
  llvm/test/CodeGen/AArch64/sve-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter-vec-plus-imm.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter-vec-plus-reg.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter.ll

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