[PATCH] D93359: [RISCV] Define vle/vse intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:87
+                    [LLVMPointerType<LLVMMatchType<0>>,
+                     llvm_anyint_ty],
+                    [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic;
----------------
liaolucy wrote:
> There are two variants of intrinsics regarding to vl, https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#vl-argument
> Any suggestions for implementing implicit vl intrinsics? What existing code can be reused?
We've been modelling this in our codebase by passing a readvl intrinsic to the vl argument of the intrinsics defined here. But that's interfering with some optimizations.

I'm not sure what the best way to implement the intrinsics that don't take a vl argument is. Since the middle end can't model the data flow of a hidden VL register we would need to mark all the intrinsics that use a hidden vl as "having side effects" so they don't get reordered around vsetvl intrinsics. The side effect flag will also prevent optimization. It also means you can't mix intrinsics that take a vl argument with intrinsics that use the current vl without also marking the intrinsics that take vl argument as having side effects.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93359/new/

https://reviews.llvm.org/D93359