[PATCH] D93284: [RISCV] Refine vector load/store tablegen pattern, NFC.

[Zakk Chen via Phabricator via llvm-commits]

khchen updated this revision to Diff 311912.
khchen added a comment.

Fix wrong index


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93284/new/

https://reviews.llvm.org/D93284

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

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