[PATCH] D93284: [RISCV] Refine vector load/store tablegen pattern, NFC.

[Kuan Hsu Chen (Zakk) via Phabricator via llvm-commits]

khchen created this revision.
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Refine tablegen pattern for vector load/store, and follow D93012 <https://reviews.llvm.org/D93012> to separate masked and unmasked definitions for pseudo load/store instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93284

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

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