[PATCH] D93272: [InstCombine] Add checking of i1 types when converting select instructions into zext/sext instructions

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp:2674
+  // zext/sext i1 to i1
+  if (SelType->isIntOrIntVectorTy() && &&!SelType->isIntOrIntVectorTy(1) &&
       CondVal->getType()->isVectorTy() == SelType->isVectorTy()) {
----------------
Extra `&&` ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93272/new/

https://reviews.llvm.org/D93272