[PATCH] D93272: [InstCombine] Add checking of i1 types when converting select instructions into zext/sext instructions

[Congzhe Cao via Phabricator via llvm-commits]

congzhe created this revision.
congzhe added reviewers: spatel, nikic, lebedev.ri, aqjune, nlopes.
congzhe added projects: fixing bugs in llvm, LLVM.
Herald added a subscriber: hiraditya.
congzhe requested review of this revision.
Herald added a subscriber: llvm-commits.

When doing select-to-zext/sext transformations, we should not handle 
TrueVal and FalseVal of i1 type otherwise it would result in zext/sext i1 to i1.

Note that the current trunk code does not break since the checking currently does exist 
but is implicit. When we have TrueVal and FalseVal of i1 type, this case will be captured 
in the previous code block: 
https://github.com/llvm/llvm-project/blob/master/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp#L2629

Therefore no unit test is provided in this patch. For maintenance purposes however, 
this patch makes the checking explicit instead of implicit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93272

Files:
  llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp


Index: llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
===================================================================
--- llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -2668,7 +2668,10 @@
   // select i1 %c, <2 x i8> <1, 1>, <2 x i8> <0, 0>
   // because that may need 3 instructions to splat the condition value:
   // extend, insertelement, shufflevector.
-  if (SelType->isIntOrIntVectorTy() &&
+  //
+  // Do not handle i1 TrueVal and FalseVal otherwise would result in
+  // zext/sext i1 to i1
+  if (SelType->isIntOrIntVectorTy() && &&!SelType->isIntOrIntVectorTy(1) &&
       CondVal->getType()->isVectorTy() == SelType->isVectorTy()) {
     // select C, 1, 0 -> zext C to int
     if (match(TrueVal, m_One()) && match(FalseVal, m_Zero()))


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