[PATCH] D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 311777.
HsiangKai added a comment.

Address @craig.topper and @evandro's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93013/new/

https://reviews.llvm.org/D93013

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll

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