[PATCH] D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics
Qing Shan Zhang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 14 18:33:16 PST 2020
steven.zhang added inline comments.
================
Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:840
+ [IntrNoMem, IntrHasSideEffects]>;
def int_ppc_altivec_vsum4sbs : GCCBuiltin<"__builtin_altivec_vsum4sbs">,
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v4i32_ty],
----------------
I think, we need to set the side effect in the .td to avoid scheduling schedule them.
```
{ 2447, 3, 1, 4, 439, 0, 0x28ULL, nullptr, nullptr, OperandInfo85 }, // Inst #2447 = VSUBUWM
{ 2448, 3, 1, 4, 376, 0, 0x28ULL, nullptr, nullptr, OperandInfo85 }, // Inst #2448 = VSUBUWS
{ 2449, 3, 1, 4, 508, 0, 0x28ULL, nullptr, nullptr, OperandInfo85 }, // Inst #2449 = VSUM2SWS
{ 2450, 3, 1, 4, 508, 0, 0x28ULL, nullptr, nullptr, OperandInfo85 }, // Inst #2450 = VSUM4SBS
{ 2451, 3, 1, 4, 508, 0, 0x28ULL, nullptr, nullptr, OperandInfo85 }, // Inst #2451 = VSUM4SHS
{ 2452, 3, 1, 4, 508, 0, 0x28ULL, nullptr, nullptr, OperandInfo85 }, // Inst #2452 = VSUM4UBS
{ 2453, 3, 1, 4, 508, 0, 0x28ULL, nullptr, nullptr, OperandInfo85 }, // Inst #2453 = VSUMSWS
```
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D90807/new/
https://reviews.llvm.org/D90807
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