[PATCH] D92951: AMDGPU: If a store defines (alias) a load, it clobbers the load.
Changpeng Fang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 14 10:57:36 PST 2020
cfang marked an inline comment as done.
cfang added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp:115
+ // Store defines the load and thus clobbers it.
+ (Q.isDef() && isa<StoreInst>(Q.getInst())))
return true;
----------------
arsenm wrote:
> cfang wrote:
> > arsenm wrote:
> > > Specifically checking for store instructions is going to be wrong since many other instruction types can also write to memory
> > Changed to mayWriteToMemory.
> Why does it need to check the instruction at all? Why isn't Q.isDef() sufficient?
Q.isDef() does not mean there must be a dependence at all.
One example is AllocaInst, in which case isDef() is returned, but the load could be optimized to undef.
I think instructional check of mayWriteToMemory is necessary here.
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https://reviews.llvm.org/D92951/new/
https://reviews.llvm.org/D92951
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