[PATCH] D93132: [SVE][CodeGen] Vector + immediate addressing mode for masked gather/scatter

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3915
+
+    BasePtr = SplatVal;
+    Index = Index->getOperand(0);
----------------
This case here (GLD1_MERGE_ZERO/SST1_PRED) seems to be the default if this function doesn't do anything, probably best not to change that.
The only case you want to handle in this function is the vector+imm case, so I think you can rewrite the control flow to something like:

  if (!isNullConstant(BasePtr))
    return false;

  ConstantSDNode *Offset = nullptr;
  if (Index.getOpcode() == ISD::ADD)
    if (auto SplatVal = DAG.getSplatValue(Index.getOperand(1))
      if (isa<ConstantSDNode>(SplatVal))
        Offset = SplatVal;

  Opcode = ....;
  if (!Offset)
    // <Swap index/opcode and return>

  // <Set index/opcode, calculate immediate and return>


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93132/new/

https://reviews.llvm.org/D93132