[PATCH] D93108: [RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:289
+  {
+    let VLMul = m.value in
+    defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m>;
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Since we're already passing "m" down to VPseudoBinary, can we just assign VLMul in VPseudoBinary?


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  https://reviews.llvm.org/D93108/new/

https://reviews.llvm.org/D93108