[PATCH] D93108: [RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
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Define vwadd/vwaddu/vwsub/vwsubu intrinsics and lower to V instructions.

In this patch, it demonstrates how to model widening vector instructions.

We work with @rogfer01 from BSC to come out this patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93108

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/vwadd.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll

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