[PATCH] D93080: [RISCV] Use tail agnostic policy for vsetvli instruction emitted in the custom inserter

[Kuan Hsu Chen (Zakk) via Phabricator via llvm-commits]

khchen added a comment.

> Maybe we should use tail undisturbed for instructions that have something like "let Constraints = "$rd = $rs3"?

Yes. It remind me that we had discussed realted issue here <https://github.com/riscv/rvv-intrinsic-doc/issues/27#issuecomment-649433549> before.

If intrinsic start to model tail behavior, when user giving a non `vundefined()` value in maskedoff argument, the tail behavior should be tail undisturbed.


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https://reviews.llvm.org/D93080