[PATCH] D93080: [RISCV] Use tail agnostic policy for vsetvli instruction emitted in the custom inserter
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 10 19:58:34 PST 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb90e2d850e78: [RISCV] Use tail agnostic policy for vsetvli instruction emitted in the custom… (authored by craig.topper).
Herald added a subscriber: jrtc27.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D93080/new/
https://reviews.llvm.org/D93080
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
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