[PATCH] D93013: [RISCV] Define vadd intrinsics and lower to V instructions.

Thu Dec 10 10:05:49 PST 2020

craig.topper added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:73

+// We only model FPR32 for V instructions in RISCVInstrInfoV.td.
+// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64
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craig.topper wrote:
> Why do we need to do this? The vector instructions for that use a FPR64 or FPR32 should only be supported when the scalar type is supported. Why can't we use the proper register class directly?
Answering my own question. SEW is part of the pseudo operands. So we don't have separate pseudos for FPR16/FPR32/FPR64. That's why we have this

I'm not completely sure about extracting FPR64 values to FPR32 when we really care about the full 64-bit value. Inserting FPR16 to FPR32 seems more ok. How many instructions does this affect?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93013/new/

https://reviews.llvm.org/D93013