[PATCH] D93048: [RISCV] Define vsub/vrsub intrinsics and refine the multiclass/class.

[Hsiangkai Wang via Phabricator via llvm-commits]

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Define vsub/vrsub intrinsics and demonstrate the organization of multiclasses and classes for pseudo instructions and patterns.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93048

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vrsub.ll
  llvm/test/CodeGen/RISCV/rvv/vsub.ll

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