[PATCH] D92842: [RFC][SelectionDAG] Add Target-Independent Compiler Barrier

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/include/llvm/Support/TargetOpcodes.def:212-215
+// This is a fence with the singlethread scope. It has a single operand, which
+// is the ordering requested. This instruction has `mayLoad` and `mayStore`, so
+// that memory operations are not moved around it.
+HANDLE_TARGET_OPCODE(COMPILER_BARRIER)
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I think the scope should also be parameterized. This also does not match the description of the defined instruction which is missing the ordering operand


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D92842/new/

https://reviews.llvm.org/D92842