[PATCH] D93013: [RISCV] Define vadd intrinsics and lower to V instructions.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2295
+  assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT ||
+          (TLI->getSubtarget().hasStdExtV() && ValVT.isScalableVector())) &&
          "Expected an XLenVT at this stage");
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I would suggest add a new assert here, the assertion message seems not fit for the extra checking.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93013/new/

https://reviews.llvm.org/D93013