[PATCH] D91048: [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

JBTW, having a need to def M0 probably defeats the idea of potential rescheduling which justifies the separation of the indirect access methods.


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  https://reviews.llvm.org/D91048/new/

https://reviews.llvm.org/D91048