[PATCH] D91048: [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:611
+  let VALU = 1;
+  let Uses = [M0, EXEC];
+}
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ruiling wrote:
> rampitec wrote:
> > ruiling wrote:
> > > We may also need "let Defs = [M0];" here? as we are changing the bits of M0 registers.
> > > And what kind of benefit we can get through adding `M0` into `Uses`?
> > > We may also need "let Defs = [M0];" here? as we are changing the bits of M0 registers.
> > 
> > I think that's right, and MODE too, plus add MODE to uses. S_SET_GPR_IDX_ON defs and uses both.
> > 
> @rampitec Thanks for a second look. I think if the new pseudo instruction only touch the mode.gpr_idx_en bit, other instructions (i.e. not s_set_gpr_idx_on/off) that modify/read the MODE register are free to schedule cross this new pseudo instruction and not having problems. So I think we may not need to add the MODE to Uses or Defs here. I am not sure if I missed some-case.
For some reason set_gpr_idx lists mode. We need to ask Matt why.


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  https://reviews.llvm.org/D91048/new/

https://reviews.llvm.org/D91048