[PATCH] D92716: [VE] Correct LVLGen (LVL instruction insert pass)

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka, craig.topper.
kaz7 added projects: LLVM, VE.
Herald added a subscriber: hiraditya.
kaz7 requested review of this revision.
Herald added a subscriber: llvm-commits.

SX Aurora VE uses an intermediate representation similar to VP as its MIR.
VE itself uses invidiual VL register as its own vector length register at
the hardware level.  So, LLVM needs to insert load VL (LVL) instruction just
before vector instructions if the value of VL is changed.  This LVLGen pass
generates LVL instructions for such purpose.  Previously, a bug is pointed
out in D91416 <https://reviews.llvm.org/D91416>.  This patch correct this bug and add a regression test.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92716

Files:
  llvm/lib/Target/VE/LVLGen.cpp
  llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll

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