[PATCH] D91092: [SVE][CodeGen] Lower scalable masked gathers
Sander de Smalen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 30 09:05:56 PST 2020
sdesmalen requested changes to this revision.
sdesmalen added inline comments.
This revision now requires changes to proceed.
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Comment at: llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll:10
+; CHECK-DAG: mov x8, xzr
+; CHECK-DAG: ld1w { z0.d }, p0/z, [x8, z0.d, lsl #2]
+; CHECK: ret
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Sorry, just spotting this now while reviewing D92319. This instruction should not use the scaled addressing mode.
That seems to be because `SelectionDAGBuilder::visitMaskedGather` defaults to `scaled`. In D90941 you've changed it to `unscaled` for MSCATTER. You'll need to do the same for MGATHER, because this leads to wrong code being generated..
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https://reviews.llvm.org/D91092/new/
https://reviews.llvm.org/D91092
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