[PATCH] D90844: [TableGen][SchedModels] Fix read/write variant substitution #2
Eugene Leviant via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 27 09:00:54 PST 2020
evgeny777 updated this revision to Diff 308072.
evgeny777 added a comment.
@dmgreen After some studying I came up with different approach: if we get rid of artifical 'AnyCPU' (zero) processor index and explicitly create one `PredTransition` per processor, we can use much simpler algorithm for variant expansion. Besides fixing read variant compilation issues this also fixes few other things:
- forwarding for sched classes with write variant (see test case)
- per-operand latency calculation when sched class (w/o InstRWs) has write variant for one operand and plain write for other operand (seems to be not present anywhere now, but may be used in future), e.g
Otherwise changes to ARM/AArch64/X86 subtargets look reasonable
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